Modern memory for a computer system is accessed with higher and higher frequencies, increasing the importance of synchronization and timing issues, in particular, when reading data from a memory. A memory controller may be utilized to provide a data transfer clock signal to a memory for clocking a data transfer from the memory to the memory controller. Due to effects on the timing of signals in the read path between the memory and the memory controller, there may occur timing shifts between the data transfer clock signal and the data received by the memory controller. Timing shifts, e.g., phase shifts between data received by a memory controller and a clock signal of the memory controller, may occur during data transfer, in particular due to differences in implementation, temperature effects and/or voltage effects. Such timing issues are of particular importance for DDR memory (double data rate memory), which requires strict control of clocking data transfer, as data is transferred both on rising and falling edges of a clock signal. Measuring and/or determining and/or correcting for such timings shifts may be considered to be calibrating data transfer between a memory and a memory controller or calibrating data transfer of a memory system. In the field of serial flash memory, in particular, DDR serial flash memory, there is not defined a standard method of calibrating the data transfer.